Design of Parallel Self-Timed Adder

Design of Parallel Self-Timed Adder

---------------------------------------------------------------------***--------------------------------------------------------------------Abstract Adders being core building blocks in different VLSI circuits like microprocessors, ALU’s etc. performance of adder circuit highly affects the overall capability of the system. In this paper we present the design and performance of Parallel Self-Tim...

Design and Analysis on High Speed Self Checking Adder Using Parallel Self Timed Adder

A brief presents a parallel single-rail self-timed adder. It is based on a recursive formulation for performing multi bit binary addition. The operation is parallel for those bits that do not need any carry chain propagation. Thus, the design attains logarithmic performance over random operand conditions without any special speedup circuitry or look-ahead schema. A practical implementation is p...

Efficient Implementation of Parallel Self-Timed Adder Using Verilog HDL

Many pipelined adaptive signal processing systems are subject to a trade-off between throughput and signal processing performance incurred by the pipelined adaptation feedback loops. In the conventional synchronous design regime, such throughput/performance trade-off is typically fixed since the pipeline depth is usually determined in the design phase and remains unchanged in the run time. Neve...

Design of Parallel Self-timer Adder without Carry Chain Propagation

Many pipelined adaptive signal processing systems are subject to a trade-off between throughput and signal processing performance incurred by the pipelined adaptation feedback loops. In the conventional synchronous design regime, such throughput/performance trade-off is typically fixed since the pipeline depth is usually determined in the design phase and remains unchanged in the run time. Neve...

Self-Timed Logic and the Design of Self-Timed Adders